1. Field of the Invention
This invention relates in general to the field of semiconductor device configuration, and more specifically to a method and apparatus that utilizes a smart fuse array on a semiconductor device to selectively enable/disable particular functional units on the device.
2. Description of the Related Art
A fuse is a circuit element with an initial structure that provides an electrical connection between two points, but which may be irreversibly destroyed thereby electrically disconnecting the two points. Fuses are sometimes used within integrated circuit devices to remove defective circuits from active operation, and to replace those defective circuits with good operable redundant circuits. Such fuses are typically fabricated in a conductive layer buried within a structure of a surrounding insulator material on the die of semiconductor device. A selected fuse is blown by directing a laser beam at the fuse, or by providing excessive electrical current to the fuse.
An example of a fuse 102 within a semiconductor circuit 100 is shown in FIG. 1. The fuse 102 is shown connected between a ground 104 and the source 106 of a FET 108. The FET 108 is configured to be "on". The source 106 is connected to a buffer 112 that is output to a particular functional block (not shown) to enable or disable the functional block. When the fuse 102 is intact, the source 106 is low, providing a logic low signal to the buffer 112. If the fuse 102 is blown, the source 106 goes high, creating a logic high signal to the buffer 112.
Thus, the circuit provides a permanent output from the buffer 112 that is either low or high, based on the condition of the fuse 102, intact or blown. The state of the fuse 102 is set at the time of manufacture, and is not modified at a later time.
To illustrate how the circuit 100 is used within a semiconductor device, reference is now made to FIG. 2. In FIG. 2, a memory device 200 is shown that includes a plurality of individually addressable memory cells 204. Also provided on the memory device 200 are a plurality of redundant memory cells 206. Each of the memory cells 206 are connected to fuse circuits 208. One skilled in the art should appreciate that not all of the memory cells 204 may be functional at the end of manufacturing. Therefore, after the device 200 has completed the manufacturing process, the memory cells 206 are tested to determine if any failures exist. Cells 210, 212 represent failed memory cells within the device 200. Fuses 208 attached to the redundant memory cells 206 on the rows associated with cells 210, 212 are blown to enable operation of those memory cells. Fuses are blown on rows where defective memory cells exist, thereby enabling associated redundant memory cells 206. Thus, by providing redundant memory cells 206, and fuse circuits 208 within the design of the device 200, defective memory cells may be selectively replaced before the device 200 is shipped to the customer. For a more complete background on the use of fuse circuits within a memory device, attention is directed to U.S. Pat. No. 5,548,555 to Lee et al., entitled METHOD AND CIRCUIT FOR REPAIRING DEFECT IN A SEMICONDUCTOR MEMORY DEVICE, the contents of which are hereby incorporated by reference.
One of the problems associated with utilizing fuse circuits to enable/disable particular functional blocks within a semiconductor device, whether a memory cell, or a complex circuit, is that once the state of the fuse is modified, i.e., by blowing the fuse, the effect on the semiconductor device is forever changed. Where fuses are used to replace defective memory cells with redundant memory cells, this is not a serious issue. However, when fuses are used to enable/disable more sophisticated functional blocks within a semiconductor device, the permanent "fused" condition is much more costly.
For example, if a fuse circuit were used to enable a floating point unit on a microprocessor, at the time of manufacture, a fuse would be blown (or left intact) to enable the FPU. All microprocessors manufactured at the same time would also have their FPU's enabled. If at some later point it was determined that the floating point unit was defective, there would be no way to disable the defective floating point unit. All of the microprocessors manufactured in that batch would have to be thrown away. This is very costly, not only for the original manufacturer, but also for all OEM's that maintained inventories of the microprocessor to build their products. One notorious example of a costly floating point unit problem required the manufacturer to provide a no questions asked replacement policy for all defective microprocessors.
Alternatively, if a particular functional block on a microprocessor is operational, but at the time of manufacture it is not desired to turn it "on", its associated fuse is blown, thereby permanently disabling the functional block. When a decision is made to turn the functional block on, currently manufactured microprocessors have their fuse left intact. However, for all of the microprocessors whose fuses are already blown, it is too late.
Moreover, as the number of functional blocks on semiconductor devices increase, so does the number of associated fuses. Requiring a one to one correspondence between functional blocks to be enabled/disabled and control fuses becomes costly, and takes up valuable die space.
What is needed is an apparatus that solves the above problems by providing an apparatus and method that allows functional blocks on semiconductor devices to be enabled/disable via a fuse array, but which also allows enablement of the functional blocks to be set to a predetermined default, or later modified through software.